1. Field of the Invention
Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to patterning processes requiring sophisticated hard mask material systems in microstructure devices.
2. Description of the Related Art
The fabrication of microstructures, such as integrated circuits, requires tiny regions of precisely controlled size to be formed in one or more material layers of an appropriate substrate, such as a silicon substrate, a silicon-on-insulator (SOI) substrate or other suitable carrier materials. These tiny regions of precisely controlled size are typically defined by patterning the material layer(s) by applying lithography, etch, implantation, deposition processes and the like, wherein, typically, at least in a certain stage of the patterning process, a mask layer may be formed over the material layer(s) to be treated to define these tiny regions. Generally, a mask layer may consist of or may be formed by means of a layer of photoresist that is patterned by a lithographic process, typically a photolithography process. During the photolithography process, the resist may be spin-coated onto the substrate surface and then selectively exposed to ultraviolet radiation through a corresponding lithography mask, such as a reticle, thereby imaging the reticle pattern into the resist layer to form a latent image therein. After developing the photoresist, depending on the type of resist, positive resist or negative resist, the exposed portions or the non-exposed portions are removed to form the required pattern in the layer of photoresist. Based on this resist pattern, actual device patterns may be formed by further manufacturing processes, such as etching, implantation, anneal processes and the like. Since the dimensions of the patterns in sophisticated integrated microstructure devices are steadily decreasing, the equipment used for patterning device features have to meet very stringent requirements with regard to resolution and overlay accuracy of the involved fabrication processes. In this respect, resolution is considered as a measure for specifying the consistent ability to print minimum size images under conditions of predefined manufacturing variations. One important factor in improving the resolution is the lithographic process, in which patterns contained in the photo mask or reticle are optically transferred to the substrate via an optical imaging system. Therefore, great efforts are made to steadily improve optical properties of the lithographic system, such as numerical aperture, depth of focus and wavelength of the light source used.
The resolution of the optical patterning process may, therefore, significantly depend on the imaging capability of the equipment used, the photoresist materials for the specified exposure wavelength and the target critical dimensions of the device features to be formed in the device level under consideration. For example, gate electrodes of field effect transistors, which represent an important component of modern logic devices, may have a length of 50 nm and less for currently produced devices, with significantly reduced dimensions for device generations that are currently under development. Similarly, the line width of metal lines provided in the plurality of wiring levels or metallization layers may also have to be adapted to the reduced feature sizes in the device layer in order to account for the increased packing density. Consequently, the actual feature dimensions may be well below the wavelength of currently used light sources implemented in current lithography systems. For example, currently in critical lithography steps, an exposure wavelength of 193 nm may be used, which, therefore, may require complex techniques for finally obtaining resist features having dimensions well below the exposure wavelength. Thus, highly non-linear processes are typically used to obtain dimensions below the optical resolution. For example, extremely non-linear photoresist materials may be used, in which a desired photochemical reaction may be initiated on the basis of a well defined threshold so that weakly exposed areas may not substantially change at all, while areas having exceeded the threshold may exhibit a significant change of their chemical stability with respect to a subsequent development process.
On the other hand, the resist material has to provide high chemical stability with respect to wet chemical and plasma enhanced etch chemistries in order to efficiently transfer a pattern of the resist mask into the underlying material layer or layers. Consequently, the resist material has to be provided with a sufficient layer thickness for a given chemical resistivity with respect to the etch chemistry in order to withstand the etch attack until a desired etch time for patterning the underlying material layers is reached. With the introduction of short wavelengths, for instance 193 nm for currently-applied exposure tools, and with the prospect of even shorter wavelengths in the foreseeable future, the resist materials have to be adapted in the photochemical composition, while, at the same time, typically, a reduced layer thickness of the resist materials may be required in view of absorbing a sufficient amount of energy within the resist material in order to reliably exceed the threshold of the resist material. On the other hand, the ever-decreasing feature sizes of sophisticated microstructure devices may result in a reduction of depth of focus on the exposure tools in order to enhance the optical resolution of these devices. Consequently, any non-uniformities in the surface topography upon applying a resist material may increasingly influence the result of the exposure process, while, in addition, the required reduced thickness of the resist material may additionally impose an increased burden on the subsequent etch process, since the reduced resist thickness may no longer provide sufficient protection of covered materials for a plurality of complex patterning processes. Since performance and reliability of sophisticated microstructure devices, such as complex integrated circuits, may strongly depend on the high degree of fidelity in transferring mask features into the material systems of the semiconductor substrate, the further scaling of microstructure devices has resulted in an increasing employment of so-called hard mask materials. Generally, a hard mask material is to be understood as a material that may provide high etch resistivity with respect to an underlying material or material system, which may be provided with a reduced layer thickness that may be readily patterned on the basis of available resist systems of reduced layer thickness. Thus, in critical patterning processes, increasingly, a stack of layers, which may include at least a hard mask material and a resist material, may be formed on the material system that is actually to be patterned, and the resist mask obtained by sophisticated lithography techniques may be used for first patterning the hard mask material, which may then provide the required etch resistivity during the further patterning of the underlying material system. In addition, frequently, the hard mask material, or at least a portion thereof, may also be used as an anti-reflective coating (ARC) material in order to reduce a back reflection of the incoming exposure energy.
Although the concept of hard mask materials may provide superior patterning results in sophisticated process strategies, this concept may be associated with several drawbacks, which may also strongly affect the patterning sequence for critical device features. For example, typical hard mask materials may be silicon nitride, silicon dioxide, silicon oxynitride and the like, since these materials are well established in semiconductor fabrication strategies and also these materials may be available for a plurality of sophisticated etch recipes in order to remove other materials selectively with respect to the hard mask material. On the other hand, these hard mask materials may have to be removed after the patterning process selectively with respect to the underlying material system, which may require a moderately high etch selectivity of the hard mask material with respect to the underlying material system, which may thus significantly restrict the applicability of the hard mask concept in critical patterning processes. Otherwise, the removal of the hard mask may have a significant influence on the finally-obtained patterning result.
In view of this situation, carbon has been considered as a viable hard mask material, since carbon has a high etch resistivity for a plurality of well-established etch recipes and may thus provide a desired high etch selectivity for a plurality of materials that are used in semiconductor fabrication processes. On the other side, carbon may be removed very efficiently by an oxygen plasma, as may also be used for resist stripping, thereby enabling the removal of the carbon material from any patterned material systems substantially without negatively affecting the underlying structure. Carbon material, for instance in the form of diamond-like carbon, may be applied by a plurality of deposition techniques, such as sputter deposition, chemical vapor deposition (CVD) and the like. In some of these deposition techniques, the carbon material may be provided with a high internal stress level, which may be considered inappropriate for a plurality of applications. Furthermore, plasma enhanced CVD techniques have been developed, in which an amorphous carbon material may be efficiently deposited on materials based on a plurality of precursor materials. For instance, many types of hydrocarbons may be used as a precursor material in combination with additional gases, such as noble gases, hydrogen and the like, thereby enabling desired high deposition rates and uniformity of the amorphous carbon material. Thus, amorphous carbon material formed on the basis of plasma enhanced CVD techniques represents a promising material for sophisticated patterning processes, possibly in combination with an overlying dielectric ARC material, which may be used for a plurality of critical patterning processes, such as the patterning of isolation trenches, gate electrode structures, contact openings in the contact level of semiconductor devices, via openings and trenches in metallization systems of complex semiconductor devices and the like.
In sophisticated patterning processes based on an amorphous carbon hard mask material, contamination problems associated with the patterning process have recently been observed, which are assumed to be caused by a reduced adhesion of the carbon material, as will be explained with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a microstructure device, such as a semiconductor device 100, in a manufacturing stage in which a material layer 102 or a material layer system may be provided above a substrate 101, such as a semiconductor material, an insulating material and the like, and has to be patterned so as to obtain device features having lateral dimensions of several hundred nanometers to tens of nanometers, depending on corresponding design rules. Thus, for instance, an opening has to be formed in the material layer 102 having a critical width as specified before and/or corresponding material regions have to be preserved, which may have a critical dimension in the above-specified range. Frequently, the material layer 102, or at least a portion thereof, may comprise a dielectric material formed on the basis of a silicon oxide material, since silicon and corresponding oxides represent well-established and frequently-used materials in the fabrication of microstructure devices. As is well known, silicon dioxide may be formed on the basis of plasma enhanced or thermally activated CVD techniques by using various precursor materials, wherein one frequently applied material is TEOS (tetraethyl orthosilicate) which may impart certain desired characteristics to the resulting silicon dioxide material. In the material layer 102 or material layer system as shown in FIG. 1a, at least an upper portion may be comprised of silicon dioxide material that is formed on the basis of TEOS. Furthermore, an amorphous carbon layer 103 is formed on the material layer 102 with a thickness of, for example, 20-60 nm. If required, a dielectric ARC layer 104, such as a silicon dioxide layer, a silicon oxynitride layer and the like, may be provided above the hard mask material 103 with a thickness of approximately 10-20 nm, depending on the optical requirements for obtaining a desired low back reflection of the entire layer stack. Furthermore, a resist mask 105 is formed above the layers 103, 104 with a thickness so as to comply with the optical requirements and provide sufficient etch resistivity for the patterning of at least the layer 104, if provided, or the layer 103. Furthermore, a mask feature, such as an opening 105A having critical dimensions as required for patterning the layer 102 is formed in the resist mask 105.
The device 100 as illustrated in FIG. 1a may be formed on the basis of well-established process techniques. That is, the layer or layer system 102 may be formed by any appropriate deposition technique, followed by a plasma enhanced CVD process for forming the amorphous carbon material 103. During the plasma enhanced deposition process, any appropriate hydrocarbon gas is supplied to the process chamber, in which a plasma may be established, for instance, on the basis of hydrogen, nitrogen, ammonia and the like. Based on appropriate process parameters, such as high frequency power, pressure and, in particular, temperature of the device 100, the layer 103 may be deposited. The selection of appropriate process parameters of the plasma enhanced CVD process may have a strong influence on the finally-obtained mechanical characteristics of the layer 103, for instance in view of adhesion to the underlying material 102. For this purpose, typically, the gas flow rate of any additional gases, generally the mixture of the various gas components, the high frequency power and, in particular, the temperature may be selected so as to obtain a high adhesion of the material 103 on the material system 102. On the other hand, many of these process parameters, such as high frequency power and temperature, may frequently not be selected independently from the specific application, since, for instance, sensitive device areas may require a restriction of one or more of these parameters. For instance, the temperature during the deposition process may not be selected above approximately 500° C., if the material layer 102 to be patterned represents a portion of a contact level or metallization system of the device 100, since any such high temperatures may negatively affect other sensitive materials, such as metal silicide regions (not shown) and the like. In other cases, an increased high frequency power may not be compatible with sensitive structures of the device 100, for instance in view of plasma damage and the like. Consequently, the process parameters used for applying the amorphous carbon material 103 may frequently represent a compromise between mechanical characteristics of the material 103 and acceptable parameter values. Thereafter, if required, the ARC material 104 may be formed on the basis of well-established process techniques, followed by the application of a resist material and a subsequent lithography process for obtaining the critical mask feature 105A.
FIG. 1b schematically illustrates the device 100 during an etch process 106 that is designed to transfer the critical mask feature 105A into the hard mask layer 103, thereby forming the feature 103A therein. As previously discussed, during the etch process 106, a significant portion of the resist material 105 may also be consumed, wherein, nevertheless, sufficient protection of covered areas of the carbon material 103 may be ensured by appropriately adapting the resist thickness. If the ARC material 104 may be provided, a very thin resist layer may be used, since in this case the resist material may have a high etch selectivity with respect to the material 104, which may then reliably protect the carbon material 103, when etched on the basis of an oxygen plasma, during which the remaining resist material may also be consumed.
Thereafter, the material system 102 may be etched on the basis of any appropriate etch chemistry, while the hard mask 103 including the mask feature 103A may provide the desired high etch resistivity. After the critical etch process, the carbon material 103 may be efficiently removed on the basis of an oxygen plasma, substantially without affecting the material 102. It has been recognized, however, that, during the various process steps, i.e., during the lithography process for patterning the resist material 105 and during the subsequent patterning of the carbon material 103, the adhesion of the material 103 to the material 102 may be insufficient, thereby causing the delamination of carbon material, which may thus result in a potential yield loss. Since the adaptation of the mechanical characteristics of the carbon material 103 may be difficult to be achieved on the basis of the process parameters of the plasma enhanced deposition process, the applicability of the per se very advantageous amorphous carbon material in critical patterning sequences may be associated with a high risk of significantly reducing production yield.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.